GPU Driver Documentation

• drm/amdgpu AMDgpu driver
  • Module Parameters
  • Core Driver Infrastructure
    • GPU Hardware Structure
      • Graphics and Compute Microcontrollers
    • Driver Structure
    • Memory Domains
    • Buffer Objects
    • PRIME Buffer Sharing
    • MMU Notifier
    • AMDGPU Virtual Memory
    • Interrupt Handling
    • IP Blocks
  • drm/amd/display - Display Core (DC)
    • AMDgpu Display Manager
      • Lifecycle
      • Interrupts
      • Atomic Implementation
      • Color Management Properties
        • DC Color Capabilities between DCN generations
      • Blend Mode Properties
        • Blend configuration flow
    • Display Core Debug tools
      • DC Visual Confirmation
        • Multiple Planes Debug
        • Pipe Split Debug
      • DTN Debug
    • Display Core Next (DCN)
      • Front End and Back End
      • Data Flow
      • AMD Hardware Pipeline
      • Global Sync
    • Multiplane Overlay (MPO)
      • Plane Restrictions
      • Cursor Restrictions
      • Use Cases
        • Picture-in-Picture (PIP) playback - Underlay strategy
        • Multiple Display MPO
          • Limitations
    • DC Glossary
  • AMDGPU XGMI Support
  • AMDGPU RAS Support
    • RAS debugfs/sysfs Control and Error Injection Interfaces
    • RAS Reboot Behavior for Unrecoverable Errors
    • RAS Error Count sysfs Interface
    • RAS EEPROM debugfs Interface
    • RAS VRAM Bad Pages sysfs Interface
    • Sample Code
  • GPU Power/Thermal Controls and Monitoring
    • HWMON Interfaces
    • GPU sysfs Power State Interfaces
      • power_dpm_state
      • power_dpm_force_performance_level
      • pp_table
      • pp_od_clk_voltage
      • pp_dpm_*
      • pp_power_profile_mode
      • *_busy_percent
      • gpu_metrics
    • GFXOFF
      • amdgpu_gfxoff
      • amdgpu_gfxoff_status
      • amdgpu_gfxoff_count
      • amdgpu_gfxoff_residency
  • Misc AMDGPU driver information
    • GPU Product Information
      • product_name
      • product_number
      • serial_number
      • unique_id
      • Accelerated Processing Units (APU) Info
      • Discrete GPU Info
    • GPU Memory Usage Information
      • mem_info_vram_total
      • mem_info_vram_used
      • mem_info_vis_vram_total
      • mem_info_vis_vram_used
      • mem_info_gtt_total
      • mem_info_gtt_used
    • PCIe Accounting Information
      • pcie_bw
      • pcie_replay_count
    • GPU SmartShift Information
      • smartshift_apu_power
      • smartshift_dgpu_power
      • smartshift_bias
  • AMDGPU Glossary
• drm/i915 Intel GFX Driver
  • Core Driver Infrastructure
    • Runtime Power Management
    • Interrupt Handling
    • Intel GVT-g Guest Support(vGPU)
    • Intel GVT-g Host Support(vGPU device model)
    • Workarounds
      • Layout
  • Display Hardware Handling
    • Mode Setting Infrastructure
    • Frontbuffer Tracking
    • Display FIFO Underrun Reporting
    • Plane Configuration
    • Atomic Plane Helpers
    • Asynchronous Page Flip
    • Output Probing
    • Hotplug
    • High Definition Audio
    • Intel HDMI LPE Audio Support
    • Panel Self Refresh PSR (PSR/SRD)
    • Frame Buffer Compression (FBC)
    • Display Refresh Rate Switching (DRRS)
    • DPIO
    • DMC Firmware Support
    • Video BIOS Table (VBT)
    • Display clocks
    • Display PLLs
    • Display State Buffer
  • GT Programming
    • Multicast/Replicated (MCR) Registers
  • Memory Management and Command Submission
    • Intel GPU Basics
    • Locking Guidelines
    • GEM BO Management Implementation Details
    • Buffer Object Eviction
    • Buffer Object Memory Shrinking
    • Batchbuffer Parsing
    • User Batchbuffer Execution
    • Scheduling
    • Logical Rings, Logical Ring Contexts and Execlists
    • Global GTT views
    • GTT Fences and Swizzling
      • Global GTT Fence Handling
      • Hardware Tiling and Swizzling Details
    • Object Tiling IOCTLs
    • Protected Objects
  • Microcontrollers
    • WOPCM
      • WOPCM Layout
    • GuC
      • GuC Firmware Layout
      • GuC Memory Management
      • GuC-specific firmware loader
      • GuC-based command submission
      • GuC ABI
    • HuC
      • HuC Memory Management
      • HuC Firmware Layout
    • DMC
  • Tracing
    • i915_ppgtt_create and i915_ppgtt_release
    • i915_context_create and i915_context_free
  • Perf
    • Overview
    • Comparison with Core Perf
      • Issues hit with first prototype based on Core Perf
    • i915 Driver Entry Points
    • i915 Perf Stream
    • i915 Perf Observation Architecture Stream
    • Other i915 Perf Internals
  • Style
    • Register macro definition style
      • File Layout
      • Naming
      • Examples
  • i915 DRM client usage stats implementation
• drm/mcde ST-Ericsson MCDE Multi-channel display engine
• drm/meson AmLogic Meson Video Processing Unit
  • Video Processing Unit
  • Video Input Unit
  • Video Post Processing
  • Video Encoder
  • Video Clocks
  • HDMI Video Output
• drm/pl111 ARM PrimeCell PL110 and PL111 CLCD Driver
• drm/tegra NVIDIA Tegra GPU and display driver
  • Driver Infrastructure
    • Host1x Infrastructure Reference
    • Host1x Syncpoint Reference
  • KMS driver
    • Display Controllers
      • Windows
    • Outputs
      • RGB/LVDS
      • HDMI
      • DSI
      • eDP/DP
  • Userspace Interface
    • GEM Buffers
    • Syncpoints
    • Command Stream Submission
• drm/tve200 Faraday TV Encoder 200
• drm/v3d Broadcom V3D Graphics Driver
  • GPU buffer object (BO) management
    • Address space management
    • GPU Scheduling
  • Interrupts
• drm/vc4 Broadcom VC4 Graphics Driver
  • Display Hardware Handling
    • Pixel Valve (DRM CRTC)
    • HVS
    • HVS planes
    • HDMI encoder
    • DSI encoder
    • DPI encoder
    • VEC (Composite TV out) encoder
  • Memory Management and 3D Command Submission
    • GPU buffer object (BO) management
    • V3D binner command list (BCL) validation
    • V3D render command list (RCL) generation
    • Shader validator for VC4
    • V3D Interrupts
• drm/vkms Virtual Kernel Modesetting
  • Setup
  • Testing With IGT
  • TODO
    • IGT better support
    • Add Plane Features
    • Runtime Configuration
    • Writeback support
    • Output Features
    • CRC API Improvements
    • Atomic Check using eBPF
• drm/bridge/dw-hdmi Synopsys DesignWare HDMI Controller
  • Synopsys DesignWare HDMI Controller
    • Supported Input Formats and Encodings
• drm/xen-front Xen para-virtualized frontend driver
  • Driver modes of operation in terms of display buffers used
    • Buffers allocated by the frontend driver
    • Buffers allocated by the backend
  • Driver limitations
• Arm Framebuffer Compression (AFBC)
  • Components and Ordering
  • Number of Planes
  • Cross-device interoperability
• drm/komeda Arm display driver
  • Overview of D71 like display IPs
    • Layer
    • Scaler
    • Compositor (compiz)
    • Writeback Layer (wb_layer)
    • Post image processor (improc)
    • Timing controller (timing_ctrlr)
    • Merger
    • Splitter
  • Possible D71 Pipeline usage
    • Single pipeline data flow
    • Dual pipeline with Slave enabled
    • Sub-pipelines for input and output
      • Layer(input) pipeline
      • Writeback(output) pipeline
      • Display output pipeline
  • Komeda Resource abstraction
    • struct komeda_pipeline/component
  • Resource discovery and initialization
  • Format handling
  • Attach komeda_dev to DRM-KMS
    • How to map plane to Layer(input) pipeline
    • Make component/pipeline to be drm_private_obj
    • Tracking component_state/pipeline_state by drm_atomic_state
    • komeda component validation
    • komeda_kms Abstraction
    • komde_kms Functions
  • Build komeda to be a Linux module driver